Mult-UIP: lpc24xx.h Source File

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00001 /******************************************************************************
00002  *   LPC24xx.h:  Header file for NXP LPC24xx Family Microprocessors
00003  *   The header file is the super set of all hardware definition of the 
00004  *   peripherals for the LPC24xx family microprocessor.
00005  *
00006  *   Copyright(C) 2006-2009, NXP Semiconductor
00007  *   All rights reserved.
00008  *
00009  *   History
00010  *   2009.03.03  ver 1.00    Prelimnary version, first Release
00011  *   2009.03.13  ver 1.01    FIO1MASK1,FIO1SET1,FIO1CLR1 value corrected
00012  *
00013 ******************************************************************************/
00014 
00015 #ifndef __LPC24xx_H
00016 #define __LPC24xx_H
00017 
00018 /* Vectored Interrupt Controller (VIC) */
00019 #define VIC_BASE_ADDR   0xFFFFF000
00020 #define VICIRQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
00021 #define VICFIQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
00022 #define VICRawIntr     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
00023 #define VICIntSelect   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C))
00024 #define VICIntEnable   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010))
00025 #define VICIntEnClr    (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014))
00026 #define VICSoftInt     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018))
00027 #define VICSoftIntClr  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C))
00028 #define VICProtection  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020))
00029 #define VICSWPrioMask  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024))
00030 
00031 #define VICVectAddr0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100))
00032 #define VICVectAddr1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104))
00033 #define VICVectAddr2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108))
00034 #define VICVectAddr3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C))
00035 #define VICVectAddr4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110))
00036 #define VICVectAddr5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114))
00037 #define VICVectAddr6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118))
00038 #define VICVectAddr7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C))
00039 #define VICVectAddr8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120))
00040 #define VICVectAddr9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124))
00041 #define VICVectAddr10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128))
00042 #define VICVectAddr11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C))
00043 #define VICVectAddr12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130))
00044 #define VICVectAddr13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134))
00045 #define VICVectAddr14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138))
00046 #define VICVectAddr15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C))
00047 #define VICVectAddr16  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140))
00048 #define VICVectAddr17  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144))
00049 #define VICVectAddr18  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148))
00050 #define VICVectAddr19  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C))
00051 #define VICVectAddr20  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150))
00052 #define VICVectAddr21  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154))
00053 #define VICVectAddr22  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158))
00054 #define VICVectAddr23  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C))
00055 #define VICVectAddr24  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160))
00056 #define VICVectAddr25  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164))
00057 #define VICVectAddr26  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168))
00058 #define VICVectAddr27  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C))
00059 #define VICVectAddr28  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170))
00060 #define VICVectAddr29  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174))
00061 #define VICVectAddr30  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178))
00062 #define VICVectAddr31  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C))
00063 
00064 /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
00065 these registers are known as "VICVectPriority(x)". */
00066 #define VICVectCntl0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
00067 #define VICVectCntl1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
00068 #define VICVectCntl2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
00069 #define VICVectCntl3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
00070 #define VICVectCntl4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
00071 #define VICVectCntl5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
00072 #define VICVectCntl6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
00073 #define VICVectCntl7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
00074 #define VICVectCntl8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
00075 #define VICVectCntl9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
00076 #define VICVectCntl10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
00077 #define VICVectCntl11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
00078 #define VICVectCntl12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
00079 #define VICVectCntl13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
00080 #define VICVectCntl14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
00081 #define VICVectCntl15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
00082 #define VICVectCntl16  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240))
00083 #define VICVectCntl17  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244))
00084 #define VICVectCntl18  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248))
00085 #define VICVectCntl19  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C))
00086 #define VICVectCntl20  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250))
00087 #define VICVectCntl21  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254))
00088 #define VICVectCntl22  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258))
00089 #define VICVectCntl23  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C))
00090 #define VICVectCntl24  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260))
00091 #define VICVectCntl25  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264))
00092 #define VICVectCntl26  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268))
00093 #define VICVectCntl27  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C))
00094 #define VICVectCntl28  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270))
00095 #define VICVectCntl29  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274))
00096 #define VICVectCntl30  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278))
00097 #define VICVectCntl31  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C))
00098 
00099 /* LPC23xx/24xx VICVectPriority(x)". */
00100 #define VICVectPriority0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
00101 #define VICVectPriority1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
00102 #define VICVectPriority2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
00103 #define VICVectPriority3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
00104 #define VICVectPriority4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
00105 #define VICVectPriority5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
00106 #define VICVectPriority6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
00107 #define VICVectPriority7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
00108 #define VICVectPriority8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
00109 #define VICVectPriority9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
00110 #define VICVectPriority10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
00111 #define VICVectPriority11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
00112 #define VICVectPriority12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
00113 #define VICVectPriority13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
00114 #define VICVectPriority14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
00115 #define VICVectPriority15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
00116 #define VICVectPriority16  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240))
00117 #define VICVectPriority17  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244))
00118 #define VICVectPriority18  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248))
00119 #define VICVectPriority19  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C))
00120 #define VICVectPriority20  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250))
00121 #define VICVectPriority21  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254))
00122 #define VICVectPriority22  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258))
00123 #define VICVectPriority23  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C))
00124 #define VICVectPriority24  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260))
00125 #define VICVectPriority25  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264))
00126 #define VICVectPriority26  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268))
00127 #define VICVectPriority27  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C))
00128 #define VICVectPriority28  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270))
00129 #define VICVectPriority29  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274))
00130 #define VICVectPriority30  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278))
00131 #define VICVectPriority31  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C))
00132 
00133 #define VICVectAddr    (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00))
00134 
00135 
00136 /* Pin Connect Block */
00137 #define PINSEL_BASE_ADDR        0xE002C000
00138 #define PINSEL0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
00139 #define PINSEL1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
00140 #define PINSEL2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08))
00141 #define PINSEL3        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C))
00142 #define PINSEL4        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10))
00143 #define PINSEL5        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
00144 #define PINSEL6        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18))
00145 #define PINSEL7        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C))
00146 #define PINSEL8        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20))
00147 #define PINSEL9        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24))
00148 #define PINSEL10       (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28))
00149 #define PINSEL11       (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x2C))
00150 
00151 #define PINMODE0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40))
00152 #define PINMODE1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44))
00153 #define PINMODE2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48))
00154 #define PINMODE3        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C))
00155 #define PINMODE4        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50))
00156 #define PINMODE5        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54))
00157 #define PINMODE6        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58))
00158 #define PINMODE7        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C))
00159 #define PINMODE8        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60))
00160 #define PINMODE9        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64))
00161 
00162 /* General Purpose Input/Output (GPIO) */
00163 #define GPIO_BASE_ADDR          0xE0028000
00164 #define IOPIN0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
00165 #define IOSET0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
00166 #define IODIR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
00167 #define IOCLR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
00168 #define IOPIN1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
00169 #define IOSET1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
00170 #define IODIR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
00171 #define IOCLR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
00172 
00173 /* GPIO Interrupt Registers */
00174 #define IO0_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) 
00175 #define IO0_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))
00176 #define IO0_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84))
00177 #define IO0_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88))
00178 #define IO0_INT_CLR     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C))
00179 
00180 #define IO2_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) 
00181 #define IO2_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4))
00182 #define IO2_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4))
00183 #define IO2_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8))
00184 #define IO2_INT_CLR     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC))
00185 
00186 #define IO_INT_STAT     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80))
00187 
00188 #define PARTCFG_BASE_ADDR               0x3FFF8000
00189 #define PARTCFG        (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) 
00190 
00191 /* Fast I/O setup */
00192 #define FIO_BASE_ADDR           0x3FFFC000
00193 #define FIO0DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) 
00194 #define FIO0MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
00195 #define FIO0PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
00196 #define FIO0SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
00197 #define FIO0CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
00198 
00199 #define FIO1DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) 
00200 #define FIO1MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
00201 #define FIO1PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
00202 #define FIO1SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
00203 #define FIO1CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
00204 
00205 #define FIO2DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) 
00206 #define FIO2MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50))
00207 #define FIO2PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54))
00208 #define FIO2SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58))
00209 #define FIO2CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C))
00210 
00211 #define FIO3DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) 
00212 #define FIO3MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70))
00213 #define FIO3PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74))
00214 #define FIO3SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))
00215 #define FIO3CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C))
00216 
00217 #define FIO4DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) 
00218 #define FIO4MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90))
00219 #define FIO4PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94))
00220 #define FIO4SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98))
00221 #define FIO4CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C))
00222 
00223 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
00224 #define FIO0DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) 
00225 #define FIO1DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) 
00226 #define FIO2DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) 
00227 #define FIO3DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) 
00228 #define FIO4DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) 
00229 
00230 #define FIO0DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) 
00231 #define FIO1DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) 
00232 #define FIO2DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) 
00233 #define FIO3DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) 
00234 #define FIO4DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) 
00235 
00236 #define FIO0DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) 
00237 #define FIO1DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) 
00238 #define FIO2DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) 
00239 #define FIO3DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) 
00240 #define FIO4DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) 
00241 
00242 #define FIO0DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) 
00243 #define FIO1DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) 
00244 #define FIO2DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) 
00245 #define FIO3DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) 
00246 #define FIO4DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) 
00247 
00248 #define FIO0DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) 
00249 #define FIO1DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) 
00250 #define FIO2DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) 
00251 #define FIO3DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) 
00252 #define FIO4DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) 
00253 
00254 #define FIO0DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) 
00255 #define FIO1DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) 
00256 #define FIO2DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) 
00257 #define FIO3DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) 
00258 #define FIO4DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) 
00259 
00260 #define FIO0MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) 
00261 #define FIO1MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) 
00262 #define FIO2MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) 
00263 #define FIO3MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) 
00264 #define FIO4MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) 
00265 
00266 #define FIO0MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) 
00267 #define FIO1MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x31)) 
00268 #define FIO2MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) 
00269 #define FIO3MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) 
00270 #define FIO4MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) 
00271 
00272 #define FIO0MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) 
00273 #define FIO1MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) 
00274 #define FIO2MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) 
00275 #define FIO3MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) 
00276 #define FIO4MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) 
00277 
00278 #define FIO0MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) 
00279 #define FIO1MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) 
00280 #define FIO2MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) 
00281 #define FIO3MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) 
00282 #define FIO4MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) 
00283 
00284 #define FIO0MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) 
00285 #define FIO1MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) 
00286 #define FIO2MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) 
00287 #define FIO3MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) 
00288 #define FIO4MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) 
00289 
00290 #define FIO0MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) 
00291 #define FIO1MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) 
00292 #define FIO2MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) 
00293 #define FIO3MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) 
00294 #define FIO4MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) 
00295 
00296 #define FIO0PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) 
00297 #define FIO1PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) 
00298 #define FIO2PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) 
00299 #define FIO3PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) 
00300 #define FIO4PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) 
00301 
00302 #define FIO0PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) 
00303 #define FIO1PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) 
00304 #define FIO2PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) 
00305 #define FIO3PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) 
00306 #define FIO4PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) 
00307 
00308 #define FIO0PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) 
00309 #define FIO1PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) 
00310 #define FIO2PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) 
00311 #define FIO3PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) 
00312 #define FIO4PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) 
00313 
00314 #define FIO0PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) 
00315 #define FIO1PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) 
00316 #define FIO2PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) 
00317 #define FIO3PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) 
00318 #define FIO4PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) 
00319 
00320 #define FIO0PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) 
00321 #define FIO1PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) 
00322 #define FIO2PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) 
00323 #define FIO3PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) 
00324 #define FIO4PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) 
00325 
00326 #define FIO0PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) 
00327 #define FIO1PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) 
00328 #define FIO2PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) 
00329 #define FIO3PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) 
00330 #define FIO4PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) 
00331 
00332 #define FIO0SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) 
00333 #define FIO1SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) 
00334 #define FIO2SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) 
00335 #define FIO3SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) 
00336 #define FIO4SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) 
00337 
00338 #define FIO0SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) 
00339 #define FIO1SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x39)) 
00340 #define FIO2SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) 
00341 #define FIO3SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) 
00342 #define FIO4SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) 
00343 
00344 #define FIO0SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) 
00345 #define FIO1SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) 
00346 #define FIO2SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) 
00347 #define FIO3SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) 
00348 #define FIO4SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) 
00349 
00350 #define FIO0SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) 
00351 #define FIO1SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) 
00352 #define FIO2SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) 
00353 #define FIO3SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) 
00354 #define FIO4SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) 
00355 
00356 #define FIO0SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) 
00357 #define FIO1SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) 
00358 #define FIO2SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) 
00359 #define FIO3SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) 
00360 #define FIO4SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) 
00361 
00362 #define FIO0SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) 
00363 #define FIO1SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) 
00364 #define FIO2SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) 
00365 #define FIO3SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) 
00366 #define FIO4SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) 
00367 
00368 #define FIO0CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) 
00369 #define FIO1CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) 
00370 #define FIO2CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) 
00371 #define FIO3CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) 
00372 #define FIO4CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) 
00373 
00374 #define FIO0CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) 
00375 #define FIO1CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3D)) 
00376 #define FIO2CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) 
00377 #define FIO3CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) 
00378 #define FIO4CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) 
00379 
00380 #define FIO0CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) 
00381 #define FIO1CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) 
00382 #define FIO2CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) 
00383 #define FIO3CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) 
00384 #define FIO4CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) 
00385 
00386 #define FIO0CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) 
00387 #define FIO1CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) 
00388 #define FIO2CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) 
00389 #define FIO3CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) 
00390 #define FIO4CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) 
00391 
00392 #define FIO0CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) 
00393 #define FIO1CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) 
00394 #define FIO2CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) 
00395 #define FIO3CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) 
00396 #define FIO4CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) 
00397 
00398 #define FIO0CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) 
00399 #define FIO1CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) 
00400 #define FIO2CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) 
00401 #define FIO3CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) 
00402 #define FIO4CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) 
00403 
00404 
00405 /* System Control Block(SCB) modules include Memory Accelerator Module,
00406 Phase Locked Loop, VPB divider, Power Control, External Interrupt, 
00407 Reset, and Code Security/Debugging */
00408 #define SCB_BASE_ADDR   0xE01FC000
00409 
00410 /* Memory Accelerator Module (MAM) */
00411 #define MAMCR          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
00412 #define MAMTIM         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
00413 #define MEMMAP         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040))
00414 
00415 /* Phase Locked Loop (PLL) */
00416 #define PLLCON         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
00417 #define PLLCFG         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
00418 #define PLLSTAT        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
00419 #define PLLFEED        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
00420 
00421 /* Power Control */
00422 #define PCON           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
00423 #define PCONP          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
00424 
00425 /* Clock Divider */
00426 // #define APBDIV         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100))
00427 #define CCLKCFG        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))
00428 #define USBCLKCFG      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))
00429 #define CLKSRCSEL      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))
00430 #define IRCTRIM        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A4))
00431 #define PCLKSEL0       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))
00432 #define PCLKSEL1       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))
00433         
00434 /* External Interrupts */
00435 #define EXTINT         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
00436 #define INTWAKE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
00437 #define EXTMODE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
00438 #define EXTPOLAR       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
00439 
00440 /* Reset, reset source identification */
00441 #define RSIR           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
00442 
00443 /* RSID, code security protection */
00444 #define CSPR           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184))
00445 
00446 /* AHB configuration */
00447 #define AHBCFG1        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188))
00448 #define AHBCFG2        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))
00449 
00450 /* System Controls and Status */
00451 #define SCS            (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))     
00452 
00453 /* MPMC(EMC) registers */
00454 #define STATIC_MEM0_BASE                0x80000000
00455 #define STATIC_MEM1_BASE                0x81000000
00456 #define STATIC_MEM2_BASE                0x82000000
00457 #define STATIC_MEM3_BASE                0x83000000
00458 
00459 #define DYNAMIC_MEM0_BASE               0xA0000000
00460 #define DYNAMIC_MEM1_BASE               0xB0000000
00461 #define DYNAMIC_MEM2_BASE               0xC0000000
00462 #define DYNAMIC_MEM3_BASE               0xD0000000
00463 
00464 /* External Memory Controller (EMC) */
00465 #define EMC_BASE_ADDR           0xFFE08000
00466 #define EMC_CTRL       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
00467 #define EMC_STAT       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
00468 #define EMC_CONFIG     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))
00469 
00470 /* Dynamic RAM access registers */
00471 #define EMC_DYN_CTRL     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))
00472 #define EMC_DYN_RFSH     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))
00473 #define EMC_DYN_RD_CFG   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))
00474 #define EMC_DYN_RP       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))
00475 #define EMC_DYN_RAS      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))
00476 #define EMC_DYN_SREX     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))
00477 #define EMC_DYN_APR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))
00478 #define EMC_DYN_DAL      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))
00479 #define EMC_DYN_WR       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044))
00480 #define EMC_DYN_RC       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))
00481 #define EMC_DYN_RFC      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))
00482 #define EMC_DYN_XSR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))
00483 #define EMC_DYN_RRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))
00484 #define EMC_DYN_MRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))
00485 
00486 #define EMC_DYN_CFG0     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))
00487 #define EMC_DYN_RASCAS0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))
00488 #define EMC_DYN_CFG1     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x120))
00489 #define EMC_DYN_RASCAS1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x124))
00490 #define EMC_DYN_CFG2     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))
00491 #define EMC_DYN_RASCAS2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))
00492 #define EMC_DYN_CFG3     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))
00493 #define EMC_DYN_RASCAS3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))
00494 
00495 /* static RAM access registers */
00496 #define EMC_STA_CFG0      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))
00497 #define EMC_STA_WAITWEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))
00498 #define EMC_STA_WAITOEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))
00499 #define EMC_STA_WAITRD0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))
00500 #define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))
00501 #define EMC_STA_WAITWR0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))
00502 #define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))
00503 
00504 #define EMC_STA_CFG1      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))
00505 #define EMC_STA_WAITWEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))
00506 #define EMC_STA_WAITOEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))
00507 #define EMC_STA_WAITRD1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))
00508 #define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))
00509 #define EMC_STA_WAITWR1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))
00510 #define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))
00511 
00512 #define EMC_STA_CFG2      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))
00513 #define EMC_STA_WAITWEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))
00514 #define EMC_STA_WAITOEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))
00515 #define EMC_STA_WAITRD2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))
00516 #define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))
00517 #define EMC_STA_WAITWR2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))
00518 #define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))
00519 
00520 #define EMC_STA_CFG3      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))
00521 #define EMC_STA_WAITWEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))
00522 #define EMC_STA_WAITOEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))
00523 #define EMC_STA_WAITRD3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))
00524 #define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))
00525 #define EMC_STA_WAITWR3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))
00526 #define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))
00527 
00528 #define EMC_STA_EXT_WAIT  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x080))
00529 
00530         
00531 /* Timer 0 */
00532 #define TMR0_BASE_ADDR          0xE0004000
00533 #define T0IR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
00534 #define T0TCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
00535 #define T0TC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
00536 #define T0PR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
00537 #define T0PC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
00538 #define T0MCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
00539 #define T0MR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
00540 #define T0MR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
00541 #define T0MR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
00542 #define T0MR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
00543 #define T0CCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
00544 #define T0CR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
00545 #define T0CR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
00546 #define T0EMR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
00547 #define T0CTCR         (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
00548 
00549 /* Timer 1 */
00550 #define TMR1_BASE_ADDR          0xE0008000
00551 #define T1IR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
00552 #define T1TCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
00553 #define T1TC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
00554 #define T1PR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
00555 #define T1PC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
00556 #define T1MCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
00557 #define T1MR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
00558 #define T1MR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
00559 #define T1MR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
00560 #define T1MR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
00561 #define T1CCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
00562 #define T1CR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
00563 #define T1CR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
00564 #define T1EMR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
00565 #define T1CTCR         (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
00566 
00567 /* Timer 2 */
00568 #define TMR2_BASE_ADDR          0xE0070000
00569 #define T2IR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
00570 #define T2TCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
00571 #define T2TC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
00572 #define T2PR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))
00573 #define T2PC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))
00574 #define T2MCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))
00575 #define T2MR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))
00576 #define T2MR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))
00577 #define T2MR2          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))
00578 #define T2MR3          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))
00579 #define T2CCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))
00580 #define T2CR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))
00581 #define T2CR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))
00582 #define T2EMR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))
00583 #define T2CTCR         (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))
00584 
00585 /* Timer 3 */
00586 #define TMR3_BASE_ADDR          0xE0074000
00587 #define T3IR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
00588 #define T3TCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
00589 #define T3TC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
00590 #define T3PR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))
00591 #define T3PC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))
00592 #define T3MCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))
00593 #define T3MR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))
00594 #define T3MR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))
00595 #define T3MR2          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))
00596 #define T3MR3          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))
00597 #define T3CCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))
00598 #define T3CR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))
00599 #define T3CR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))
00600 #define T3EMR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))
00601 #define T3CTCR         (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))
00602 
00603 
00604 /* Pulse Width Modulator (PWM) */
00605 #define PWM0_BASE_ADDR          0xE0014000
00606 #define PWM0IR          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00))
00607 #define PWM0TCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04))
00608 #define PWM0TC          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08))
00609 #define PWM0PR          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C))
00610 #define PWM0PC          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10))
00611 #define PWM0MCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14))
00612 #define PWM0MR0         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18))
00613 #define PWM0MR1         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C))
00614 #define PWM0MR2         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20))
00615 #define PWM0MR3         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24))
00616 #define PWM0CCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28))
00617 #define PWM0CR0         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C))
00618 #define PWM0CR1         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30))
00619 #define PWM0MR4         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40))
00620 #define PWM0MR5         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44))
00621 #define PWM0MR6         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48))
00622 #define PWM0PCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C))
00623 #define PWM0LER         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50))
00624 #define PWM0CTCR        (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70))
00625 
00626 #define PWM1_BASE_ADDR          0xE0018000
00627 #define PWM1IR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
00628 #define PWM1TCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
00629 #define PWM1TC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
00630 #define PWM1PR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))
00631 #define PWM1PC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))
00632 #define PWM1MCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))
00633 #define PWM1MR0         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))
00634 #define PWM1MR1         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))
00635 #define PWM1MR2         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))
00636 #define PWM1MR3         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))
00637 #define PWM1CCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))
00638 #define PWM1CR0         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))
00639 #define PWM1CR1         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))
00640 #define PWM1MR4         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))
00641 #define PWM1MR5         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))
00642 #define PWM1MR6         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))
00643 #define PWM1PCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))
00644 #define PWM1LER         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))
00645 #define PWM1CTCR        (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))
00646 
00647 
00648 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
00649 #define UART0_BASE_ADDR         0xE000C000
00650 #define U0RBR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00651 #define U0THR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00652 #define U0DLL          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00653 #define U0DLM          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00654 #define U0IER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00655 #define U0IIR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00656 #define U0FCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00657 #define U0LCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
00658 #define U0LSR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))
00659 #define U0SCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))
00660 #define U0ACR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))
00661 #define U0ICR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24))
00662 #define U0FDR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))
00663 #define U0TER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
00664 
00665 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
00666 #define UART1_BASE_ADDR         0xE0010000
00667 #define U1RBR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00668 #define U1THR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00669 #define U1DLL          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00670 #define U1DLM          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00671 #define U1IER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00672 #define U1IIR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00673 #define U1FCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00674 #define U1LCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
00675 #define U1MCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))
00676 #define U1LSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))
00677 #define U1MSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
00678 #define U1SCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
00679 #define U1ACR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
00680 #define U1FDR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
00681 #define U1TER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
00682 
00683 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
00684 #define UART2_BASE_ADDR         0xE0078000
00685 #define U2RBR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
00686 #define U2THR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
00687 #define U2DLL          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
00688 #define U2DLM          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
00689 #define U2IER          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
00690 #define U2IIR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
00691 #define U2FCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
00692 #define U2LCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))
00693 #define U2LSR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))
00694 #define U2SCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))
00695 #define U2ACR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))
00696 #define U2ICR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24))
00697 #define U2FDR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))
00698 #define U2TER          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))
00699 
00700 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
00701 #define UART3_BASE_ADDR         0xE007C000
00702 #define U3RBR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
00703 #define U3THR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
00704 #define U3DLL          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
00705 #define U3DLM          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
00706 #define U3IER          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
00707 #define U3IIR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
00708 #define U3FCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
00709 #define U3LCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))
00710 #define U3LSR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))
00711 #define U3SCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))
00712 #define U3ACR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))
00713 #define U3ICR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))
00714 #define U3FDR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))
00715 #define U3TER          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))
00716 
00717 /* I2C Interface 0 */
00718 #define I2C0_BASE_ADDR          0xE001C000
00719 #define I20CONSET      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
00720 #define I20STAT        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
00721 #define I20DAT         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
00722 #define I20ADR         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
00723 #define I20SCLH        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
00724 #define I20SCLL        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
00725 #define I20CONCLR      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
00726 
00727 /* I2C Interface 1 */
00728 #define I2C1_BASE_ADDR          0xE005C000
00729 #define I21CONSET      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
00730 #define I21STAT        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
00731 #define I21DAT         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
00732 #define I21ADR         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
00733 #define I21SCLH        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
00734 #define I21SCLL        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
00735 #define I21CONCLR      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
00736 
00737 /* I2C Interface 2 */
00738 #define I2C2_BASE_ADDR          0xE0080000
00739 #define I22CONSET      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))
00740 #define I22STAT        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))
00741 #define I22DAT         (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))
00742 #define I22ADR         (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))
00743 #define I22SCLH        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))
00744 #define I22SCLL        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))
00745 #define I22CONCLR      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))
00746 
00747 /* SPI0 (Serial Peripheral Interface 0) */
00748 #define SPI0_BASE_ADDR          0xE0020000
00749 #define S0SPCR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
00750 #define S0SPSR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
00751 #define S0SPDR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
00752 #define S0SPCCR        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
00753 #define S0SPINT        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
00754 
00755 /* SSP0 Controller */
00756 #define SSP0_BASE_ADDR          0xE0068000
00757 #define SSP0CR0        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))
00758 #define SSP0CR1        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))
00759 #define SSP0DR         (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))
00760 #define SSP0SR         (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))
00761 #define SSP0CPSR       (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))
00762 #define SSP0IMSC       (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))
00763 #define SSP0RIS        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))
00764 #define SSP0MIS        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))
00765 #define SSP0ICR        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))
00766 #define SSP0DMACR      (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))
00767 
00768 /* SSP1 Controller */
00769 #define SSP1_BASE_ADDR          0xE0030000
00770 #define SSP1CR0        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))
00771 #define SSP1CR1        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))
00772 #define SSP1DR         (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))
00773 #define SSP1SR         (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))
00774 #define SSP1CPSR       (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))
00775 #define SSP1IMSC       (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))
00776 #define SSP1RIS        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))
00777 #define SSP1MIS        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))
00778 #define SSP1ICR        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))
00779 #define SSP1DMACR      (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))
00780 
00781 
00782 /* Real Time Clock */
00783 #define RTC_BASE_ADDR           0xE0024000
00784 #define RTC_ILR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
00785 #define RTC_CTC         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
00786 #define RTC_CCR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
00787 #define RTC_CIIR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
00788 #define RTC_AMR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
00789 #define RTC_CTIME0      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
00790 #define RTC_CTIME1      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
00791 #define RTC_CTIME2      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
00792 #define RTC_SEC         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
00793 #define RTC_MIN         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
00794 #define RTC_HOUR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
00795 #define RTC_DOM         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
00796 #define RTC_DOW         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
00797 #define RTC_DOY         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
00798 #define RTC_MONTH       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
00799 #define RTC_YEAR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
00800 #define RTC_CISS        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))
00801 #define RTC_ALSEC       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
00802 #define RTC_ALMIN       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
00803 #define RTC_ALHOUR      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
00804 #define RTC_ALDOM       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
00805 #define RTC_ALDOW       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
00806 #define RTC_ALDOY       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
00807 #define RTC_ALMON       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
00808 #define RTC_ALYEAR      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
00809 #define RTC_PREINT      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))
00810 #define RTC_PREFRAC     (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
00811 
00812 
00813 /* A/D Converter 0 (AD0) */
00814 #define AD0_BASE_ADDR           0xE0034000
00815 #define AD0CR          (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
00816 #define AD0GDR         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
00817 #define AD0INTEN       (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
00818 #define AD0DR0         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
00819 #define AD0DR1         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
00820 #define AD0DR2         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
00821 #define AD0DR3         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
00822 #define AD0DR4         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
00823 #define AD0DR5         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
00824 #define AD0DR6         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
00825 #define AD0DR7         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
00826 #define AD0STAT        (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
00827 
00828 
00829 /* D/A Converter */
00830 #define DAC_BASE_ADDR           0xE006C000
00831 #define DACR           (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
00832 
00833 
00834 /* Watchdog */
00835 #define WDG_BASE_ADDR           0xE0000000
00836 #define WDMOD          (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
00837 #define WDTC           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
00838 #define WDFEED         (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
00839 #define WDTV           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
00840 #define WDCLKSEL       (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10))
00841 
00842 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
00843 #define CAN_ACCEPT_BASE_ADDR            0xE003C000
00844 #define CAN_AFMR                (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))      
00845 #define CAN_SFF_SA              (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))      
00846 #define CAN_SFF_GRP_SA  (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
00847 #define CAN_EFF_SA              (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
00848 #define CAN_EFF_GRP_SA  (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))      
00849 #define CAN_EOT                 (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))
00850 #define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))      
00851 #define CAN_LUT_ERR     (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
00852 
00853 #define CAN_CENTRAL_BASE_ADDR           0xE0040000      
00854 #define CAN_TX_SR       (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))     
00855 #define CAN_RX_SR       (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))     
00856 #define CAN_MSR         (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
00857 
00858 #define CAN1_BASE_ADDR          0xE0044000
00859 #define CAN1MOD         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))    
00860 #define CAN1CMR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))    
00861 #define CAN1GSR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))    
00862 #define CAN1ICR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))    
00863 #define CAN1IER         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
00864 #define CAN1BTR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))    
00865 #define CAN1EWL         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))    
00866 #define CAN1SR          (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))    
00867 #define CAN1RFS         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))    
00868 #define CAN1RID         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
00869 #define CAN1RDA         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))    
00870 #define CAN1RDB         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
00871         
00872 #define CAN1TFI1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))    
00873 #define CAN1TID1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))    
00874 #define CAN1TDA1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
00875 #define CAN1TDB1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))    
00876 #define CAN1TFI2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))    
00877 #define CAN1TID2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))    
00878 #define CAN1TDA2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))    
00879 #define CAN1TDB2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
00880 #define CAN1TFI3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))    
00881 #define CAN1TID3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))    
00882 #define CAN1TDA3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))    
00883 #define CAN1TDB3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
00884 
00885 #define CAN2_BASE_ADDR          0xE0048000
00886 #define CAN2MOD         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))    
00887 #define CAN2CMR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))    
00888 #define CAN2GSR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))    
00889 #define CAN2ICR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))    
00890 #define CAN2IER         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
00891 #define CAN2BTR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))    
00892 #define CAN2EWL         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))    
00893 #define CAN2SR          (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))    
00894 #define CAN2RFS         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))    
00895 #define CAN2RID         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
00896 #define CAN2RDA         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))    
00897 #define CAN2RDB         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
00898         
00899 #define CAN2TFI1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))    
00900 #define CAN2TID1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))    
00901 #define CAN2TDA1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
00902 #define CAN2TDB1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))    
00903 #define CAN2TFI2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))    
00904 #define CAN2TID2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))    
00905 #define CAN2TDA2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))    
00906 #define CAN2TDB2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
00907 #define CAN2TFI3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))    
00908 #define CAN2TID3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))    
00909 #define CAN2TDA3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))    
00910 #define CAN2TDB3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
00911 
00912 
00913 /* MultiMedia Card Interface(MCI) Controller */
00914 #define MCI_BASE_ADDR           0xE008C000
00915 #define MCI_POWER      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00))
00916 #define MCI_CLOCK      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04))
00917 #define MCI_ARGUMENT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08))
00918 #define MCI_COMMAND    (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C))
00919 #define MCI_RESP_CMD   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10))
00920 #define MCI_RESP0      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14))
00921 #define MCI_RESP1      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18))
00922 #define MCI_RESP2      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C))
00923 #define MCI_RESP3      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20))
00924 #define MCI_DATA_TMR   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24))
00925 #define MCI_DATA_LEN   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28))
00926 #define MCI_DATA_CTRL  (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C))
00927 #define MCI_DATA_CNT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30))
00928 #define MCI_STATUS     (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34))
00929 #define MCI_CLEAR      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38))
00930 #define MCI_MASK0      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C))
00931 #define MCI_MASK1      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40))
00932 #define MCI_FIFO_CNT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48))
00933 #define MCI_FIFO       (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80))
00934 
00935 
00936 /* I2S Interface Controller (I2S) */
00937 #define I2S_BASE_ADDR           0xE0088000
00938 #define I2S_DAO        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
00939 #define I2S_DAI        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
00940 #define I2S_TX_FIFO    (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
00941 #define I2S_RX_FIFO    (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))
00942 #define I2S_STATE      (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))
00943 #define I2S_DMA1       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))
00944 #define I2S_DMA2       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))
00945 #define I2S_IRQ        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))
00946 #define I2S_TXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))
00947 #define I2S_RXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))
00948 
00949 
00950 /* General-purpose DMA Controller */
00951 #define DMA_BASE_ADDR           0xFFE04000
00952 #define GPDMA_INT_STAT         (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
00953 #define GPDMA_INT_TCSTAT       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
00954 #define GPDMA_INT_TCCLR        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
00955 #define GPDMA_INT_ERR_STAT     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))
00956 #define GPDMA_INT_ERR_CLR      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))
00957 #define GPDMA_RAW_INT_TCSTAT   (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))
00958 #define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))
00959 #define GPDMA_ENABLED_CHNS     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))
00960 #define GPDMA_SOFT_BREQ        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))
00961 #define GPDMA_SOFT_SREQ        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))
00962 #define GPDMA_SOFT_LBREQ       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))
00963 #define GPDMA_SOFT_LSREQ       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))
00964 #define GPDMA_CONFIG           (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))
00965 #define GPDMA_SYNC             (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))
00966 
00967 /* DMA channel 0 registers */
00968 #define GPDMA_CH0_SRC      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))
00969 #define GPDMA_CH0_DEST     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))
00970 #define GPDMA_CH0_LLI      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))
00971 #define GPDMA_CH0_CTRL     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))
00972 #define GPDMA_CH0_CFG      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))
00973 
00974 /* DMA channel 1 registers */
00975 #define GPDMA_CH1_SRC      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))
00976 #define GPDMA_CH1_DEST     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))
00977 #define GPDMA_CH1_LLI      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))
00978 #define GPDMA_CH1_CTRL     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))
00979 #define GPDMA_CH1_CFG      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))
00980 
00981 
00982 /* USB Controller */
00983 #define USB_INT_BASE_ADDR       0xE01FC1C0
00984 #define USB_BASE_ADDR           0xFFE0C200              /* USB Base Address */
00985 
00986 #define USB_INT_STAT    (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))
00987 
00988 /* USB Device Interrupt Registers */
00989 #define DEV_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
00990 #define DEV_INT_EN      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
00991 #define DEV_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
00992 #define DEV_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
00993 #define DEV_INT_PRIO    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))
00994 
00995 /* USB Device Endpoint Interrupt Registers */
00996 #define EP_INT_STAT     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
00997 #define EP_INT_EN       (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
00998 #define EP_INT_CLR      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
00999 #define EP_INT_SET      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
01000 #define EP_INT_PRIO     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))
01001 
01002 /* USB Device Endpoint Realization Registers */
01003 #define REALIZE_EP      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
01004 #define EP_INDEX        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
01005 #define MAXPACKET_SIZE  (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))
01006 
01007 /* USB Device Command Reagisters */
01008 #define CMD_CODE        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
01009 #define CMD_DATA        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))
01010 
01011 /* USB Device Data Transfer Registers */
01012 #define RX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
01013 #define TX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
01014 #define RX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
01015 #define TX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
01016 #define USB_CTRL        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))
01017 
01018 /* USB Device DMA Registers */
01019 #define DMA_REQ_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50))
01020 #define DMA_REQ_CLR         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54))
01021 #define DMA_REQ_SET         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58))
01022 #define UDCA_HEAD           (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80))
01023 #define EP_DMA_STAT         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84))
01024 #define EP_DMA_EN           (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88))
01025 #define EP_DMA_DIS          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C))
01026 #define DMA_INT_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90))
01027 #define DMA_INT_EN          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94))
01028 #define EOT_INT_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0))
01029 #define EOT_INT_CLR         (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4))
01030 #define EOT_INT_SET         (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8))
01031 #define NDD_REQ_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC))
01032 #define NDD_REQ_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0))
01033 #define NDD_REQ_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4))
01034 #define SYS_ERR_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8))
01035 #define SYS_ERR_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC))
01036 #define SYS_ERR_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0))
01037 
01038 /* USB Host Controller */
01039 #define USBHC_BASE_ADDR         0xFFE0C000
01040 #define HC_REVISION         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00))
01041 #define HC_CONTROL          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04))
01042 #define HC_CMD_STAT         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08))
01043 #define HC_INT_STAT         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C))
01044 #define HC_INT_EN           (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10))
01045 #define HC_INT_DIS          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14))
01046 #define HC_HCCA             (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18))
01047 #define HC_PERIOD_CUR_ED    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C))
01048 #define HC_CTRL_HEAD_ED     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20))
01049 #define HC_CTRL_CUR_ED      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24))
01050 #define HC_BULK_HEAD_ED     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28))
01051 #define HC_BULK_CUR_ED      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C))
01052 #define HC_DONE_HEAD        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30))
01053 #define HC_FM_INTERVAL      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34))
01054 #define HC_FM_REMAINING     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38))
01055 #define HC_FM_NUMBER        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C))
01056 #define HC_PERIOD_START     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40))
01057 #define HC_LS_THRHLD        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44))
01058 #define HC_RH_DESCA         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48))
01059 #define HC_RH_DESCB         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C))
01060 #define HC_RH_STAT          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50))
01061 #define HC_RH_PORT_STAT1    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54))
01062 #define HC_RH_PORT_STAT2    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58))
01063 
01064 /* USB OTG Controller */
01065 #define USBOTG_BASE_ADDR        0xFFE0C100
01066 #define OTG_INT_STAT        (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00))
01067 #define OTG_INT_EN          (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04))
01068 #define OTG_INT_SET         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08))
01069 #define OTG_INT_CLR         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C))
01070 #define OTG_STAT_CTRL       (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
01071 #define OTG_TIMER           (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14))
01072 
01073 #define USBOTG_I2C_BASE_ADDR    0xFFE0C300
01074 #define OTG_I2C_RX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
01075 #define OTG_I2C_TX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
01076 #define OTG_I2C_STS         (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04))
01077 #define OTG_I2C_CTL         (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08))
01078 #define OTG_I2C_CLKHI       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C))
01079 #define OTG_I2C_CLKLO       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10))
01080 
01081 #define USBOTG_CLK_BASE_ADDR    0xFFE0CFF0
01082 #define OTG_CLK_CTRL        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
01083 #define OTG_CLK_STAT        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
01084 
01085 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
01086 #define MAC_BASE_ADDR           0xFFE00000 /* AHB Peripheral # 0 */
01087 #define MAC_MAC1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
01088 #define MAC_MAC2            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
01089 #define MAC_IPGT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
01090 #define MAC_IPGR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
01091 #define MAC_CLRT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
01092 #define MAC_MAXF            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
01093 #define MAC_SUPP            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
01094 #define MAC_TEST            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
01095 #define MAC_MCFG            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
01096 #define MAC_MCMD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
01097 #define MAC_MADR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
01098 #define MAC_MWTD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
01099 #define MAC_MRDD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
01100 #define MAC_MIND            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
01101 
01102 #define MAC_SA0             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
01103 #define MAC_SA1             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
01104 #define MAC_SA2             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
01105 
01106 #define MAC_COMMAND         (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
01107 #define MAC_STATUS          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
01108 #define MAC_RXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
01109 #define MAC_RXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
01110 #define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
01111 #define MAC_RXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
01112 #define MAC_RXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
01113 #define MAC_TXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
01114 #define MAC_TXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
01115 #define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
01116 #define MAC_TXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
01117 #define MAC_TXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
01118 
01119 #define MAC_TSV0            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
01120 #define MAC_TSV1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
01121 #define MAC_RSV             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
01122 
01123 #define MAC_FLOWCONTROLCNT  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
01124 #define MAC_FLOWCONTROLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
01125 
01126 #define MAC_RXFILTERCTRL    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
01127 #define MAC_RXFILTERWOLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
01128 #define MAC_RXFILTERWOLCLR  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
01129 
01130 #define MAC_HASHFILTERL     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
01131 #define MAC_HASHFILTERH     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
01132 
01133 #define MAC_INTSTATUS       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
01134 #define MAC_INTENABLE       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg  */
01135 #define MAC_INTCLEAR        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
01136 #define MAC_INTSET          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
01137 
01138 #define MAC_POWERDOWN       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
01139 #define MAC_MODULEID        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
01140 
01141 /* LCD Controller registers */
01142 #define LCD_BASE_ADDR           0xFFE10000 /* AHB Peripheral # 4 */
01143 #define LCD_CFG             (*(volatile unsigned long *)(0xE01FC1B8))
01144 #define LCD_TIMH            (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000))
01145 #define LCD_TIMV            (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004))
01146 #define LCD_POL             (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x008))
01147 #define LCD_LE              (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x00C))
01148 #define LCD_UPBASE          (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x010))
01149 #define LCD_LPBASE          (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x014))
01150 #define LCD_CTRL            (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x018))
01151 #define LCD_INTMSK          (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x01C))
01152 #define LCD_INTRAW          (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x020))
01153 #define LCD_INTSTAT         (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x024))
01154 #define LCD_INTCLR          (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x028))
01155 #define LCD_UPCURR          (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x02C))
01156 #define LCD_LPCURR          (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x030))
01157 #define LCD_PAL             (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x200))
01158 #define CRSR_IMG            (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x800))
01159 #define CRSR_CTRL           (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC00))
01160 #define CRSR_CFG            (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC04))
01161 #define CRSR_PAL0           (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC08))
01162 #define CRSR_PAL1           (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC0C))
01163 #define CRSR_XY             (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC10))
01164 #define CRSR_CLIP           (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC14))
01165 #define CRSR_INTMSK         (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC20))
01166 #define CRSR_INTCLR         (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC24))
01167 #define CRSR_INTRAW         (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC28))
01168 #define CRSR_INTSTAT        (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC2C))
01169 
01170 
01171 #endif  // __LPC24xx_H
01172