i2c_isr.c

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00001 
00011 /*
00012  * i2c_isr.c
00013  *
00014  *  Created on: 07/01/2011
00015  *      Author: fanl
00016  */
00017 
00018 #include "../lpc_config.h"
00019 #include "i2c.h"
00020 #include "../uart/uart.h"
00021 
00022 extern volatile int I2CMasterState;
00023 extern volatile int I2CCmd;
00024 extern volatile char I2CMasterBuffer[BUFSIZE];
00025 extern volatile int I2CReadLength;
00026 extern volatile int I2CWriteLength;
00027 extern volatile int RdIndex;
00028 extern volatile int WrIndex;
00029 
00030 
00031 void I2C0MasterHandler( void ) __attribute__ ((interrupt("IRQ")));
00032 
00033 /*****************************************************************************
00034 ** Function name:               I2C0MasterHandler
00035 **
00036 ** Descriptions:                I2C0 interrupt handler, deal with master mode
00037 **                              only.
00038 **
00039 ** parameters:                  None
00040 ** Returned value:              None
00041 **
00042 *****************************************************************************/
00043 void I2C0MasterHandler(void)
00044 {
00045   char StatValue;
00046   uart_putc('i');
00047   /* this handler deals with master read and master write only */
00048   StatValue = I22STAT;
00049   switch ( StatValue )
00050   {
00051         case 0x08:                      /* A Start condition is issued. */
00052         I22DAT = I2CMasterBuffer[0];
00053         I22CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC);
00054         I2CMasterState = I2C_STARTED;
00055         break;
00056 
00057         case 0x10:                      /* A repeated started is issued */
00058         if ( I2CCmd == LM75_TEMP )
00059         {
00060           I22DAT = I2CMasterBuffer[2];
00061         }
00062         I22CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC);
00063         I2CMasterState = I2C_RESTARTED;
00064         break;
00065 
00066         case 0x18:                      /* Regardless, it's a ACK */
00067         if ( I2CMasterState == I2C_STARTED )
00068         {
00069           I22DAT = I2CMasterBuffer[1+WrIndex];
00070           WrIndex++;
00071           I2CMasterState = DATA_ACK;
00072         }
00073         I22CONCLR = I2CONCLR_SIC;
00074         break;
00075 
00076         case 0x28:      /* Data char has been transmitted, regardless ACK or NACK */
00077         case 0x30:
00078         if ( WrIndex != I2CWriteLength )
00079         {
00080           I22DAT = I2CMasterBuffer[1+WrIndex]; /* this should be the last one */
00081           WrIndex++;
00082           if ( WrIndex != I2CWriteLength )
00083           {
00084                 I2CMasterState = DATA_ACK;
00085           }
00086           else
00087           {
00088                 I2CMasterState = DATA_NACK;
00089                 if ( I2CReadLength != 0 )
00090                 {
00091                   I22CONSET = I2CONSET_STA;     /* Set Repeated-start flag */
00092                   I2CMasterState = I2C_REPEATED_START;
00093                 }
00094           }
00095         }
00096         else
00097         {
00098           if ( I2CReadLength != 0 )
00099           {
00100                 I22CONSET = I2CONSET_STA;       /* Set Repeated-start flag */
00101                 I2CMasterState = I2C_REPEATED_START;
00102           }
00103           else
00104           {
00105                 I2CMasterState = DATA_NACK;
00106                 I22CONSET = I2CONSET_STO;      /* Set Stop flag */
00107           }
00108         }
00109         I22CONCLR = I2CONCLR_SIC;
00110         break;
00111 
00112         case 0x40:      /* Master Receive, SLA_R has been sent */
00113         I22CONSET = I2CONSET_AA;        /* assert ACK after data is received */
00114         I22CONCLR = I2CONCLR_SIC;
00115         break;
00116 
00117         case 0x50:      /* Data char has been received, regardless following ACK or NACK */
00118         case 0x58:
00119         I2CMasterBuffer[3+RdIndex] = I22DAT;
00120         RdIndex++;
00121         if ( RdIndex != I2CReadLength )
00122         {
00123           I2CMasterState = DATA_ACK;
00124         }
00125         else
00126         {
00127           RdIndex = 0;
00128           I2CMasterState = DATA_NACK;
00129         }
00130         I22CONSET = I2CONSET_AA;        /* assert ACK after data is received */
00131         I22CONCLR = I2CONCLR_SIC;
00132         break;
00133 
00134         case 0x20:              /* regardless, it's a NACK */
00135         case 0x48:
00136         I22CONCLR = I2CONCLR_SIC;
00137         I2CMasterState = DATA_NACK;
00138         break;
00139 
00140         case 0x38:              /* Arbitration lost, in this example, we don't
00141                                         deal with multiple master situation */
00142         default:
00143         I22CONCLR = I2CONCLR_SIC;
00144         break;
00145   }
00146   VICVectAddr = 0;              /* Acknowledge Interrupt */
00147 }